The present invention relates to an equalizer and a terminal device for mobile communications, and more particularly to an equalizer having a filter coefficient setting circuit, and a terminal device with such an equalizer for mobile communications.
High-speed code transmission systems such as digital radio telephone systems suffer a delayed dispersion due to multipath propagations, often bringing about fading. As a result, terminal devices for mobile communications have reception characteristics greatly degraded by such fading.
For solving the above problems, it is effective to use an adaptive equalizer which adapts itself to changing transmission path characteristics. To obtain better equalization characteristics when the transmission path has its characteristics changing rapidly, it is important that the adaptive equalizer be capable of sufficiently adapting itself to rapidly changing transmission path characteristics.
FIG. 1 of the accompanying drawings shows a receiving system having an equalizer in a terminal device for a mobile communications system such as a digital radio telephone system.
As shown in FIG. 1, the receiving system comprises an antenna 301, a local oscillator A 302, a frequency converter 303, a bandpass filter 304, a local oscillator B 305, a frequency converter 306, a correlator 307, a synchronizing circuit 308, an A/D converter 309, an equalizer 310, and an output terminal 311.
An RF signal (a) received by the antenna 301, which represents a transmitted signal that has been modulated by .pi./4-shift DQPSK is supplied to an input terminal of the frequency converter 303. The frequency converter 303 converts the frequency of the RF signal (a) into an IF (intermediate frequency) signal (b) using a signal that is supplied from the local oscillator A 302 to another input terminal of the frequency converter 303.
The frequency converter 303 outputs an IF signal to the bandpass filter 304, which removes noise from the signal band to produce an band-limited IF signal (c) .
The IF signal (c) is supplied to an input terminal of the frequency converter 306. The frequency converter 306 converts the frequency of the IF signal (c) into a baseband signal (d) using a signal that is supplied from the local oscillator B 305 to another input terminal of the frequency converter 306.
The baseband signal (d) output from the frequency converter 306 is supplied to the correlator 307 and the A/D converter 309.
The correlator 307, which serves to remove effects of fading from the baseband signal (d) , supplies its output signal to the synchronizing circuit 308. The synchronizing circuit 308 generates a sample timing signal (e) and supplies the sample timing signal (e) to the A/D converter 309.
Based on the supplied sample timing signal (e), the A/D converter 309 samples the baseband signal (d) supplied from the frequency converter 306 and converts the sampled baseband signal (d) into a digital signal. The digital signal from the A/D converter 309 is supplied to the equalizer 310.
Prior to describing details of the equalizer 310, the signal receiving operation of the receiving system shown in FIG. 1 which has a bearing on the present invention will briefly be described below.
A signal transmitted over a transmission path is a signal including a training signal composed of known symbols as shown in FIG. 2 of the accompanying drawings. In the receiving system, the training signal is detected on the basis of the known symbols, and tap coefficients of the equalizer 310 are converged and established on the basis of the detected training signal. After the training signal, the equalizer 310 updates the tap coefficients that have been converged upon training, thereby to adapt itself to changing transmission path characteristics.
The equalizer 310 will now be described in detail with respect to its arrangement and operation. FIG. 3 of the accompanying drawings shows, by way of example, of details of a linear equalizer (LE).
As shown in FIG. 3, the equalizer, generally denoted by 500, has a signal input terminal 501, a transversal filter 502, a symbol determining circuit 503, a signal output terminal 504, a subtractor 505, and a tap coefficient setting circuit 506.
The transversal filter 502 comprises a plurality of series-connected delay elements T.sub.1 .about.T.sub.n-1, a plurality of tap lines t.sub.O .about.t.sub.n-1 extending respectively from the delay elements T.sub.1 .about.T.sub.n-1, a plurality of coefficient units h.sub.0 .about.h.sub.n-1, and a plurality of adders a.sub.0 .about.a.sub.n-1.
A series digital signal (f) supplied to the signal input terminal 501 is delayed successively by the (n-1) delay elements T.sub.1 .about.T.sub.n-1, and extracted in parallel from the n tap lines t.sub.0 .about.t.sub.n-1 which extend from the input and output terminals of the delay elements T.sub.1 .about.T.sub.n-1. The signals from the tap lines t.sub.O .about.t.sub.n-1 are weighted by the corresponding coefficient units h.sub.0 .about.h.sub.n-1, and added by the adders a.sub.0 .about.a.sub.n-1 into a single line that is supplied to the symbol determining circuit 503.
Since symbols are shifted from normal phase points of .pi./4-shift DQPSK in the transversal filter 502 due to fading, the symbol determining circuit 503 determines the symbols of an output signal from the transversal filter 502, and outputs symbols corresponding to the respective normal phase points of .pi./4-shift DQPSK.
The subtractor 505 calculates the difference between an output signal (q) from the transversal filter 502 and an output signal (i) from the symbol determining circuit 503, and applies a differential signal (j) to the tap coefficient setting circuit 506. Based on the differential signal (j) from the subtractor 505, the tap coefficient setting circuit 506 estimates tap coefficients and generates control signals e.sub.0 .about.e.sub.n-1 for establishing the estimated tap coefficients. The control signals e.sub.0 .about.e.sub.n-1 from the tap coefficient setting circuit 506 are supplied to the corresponding coefficient units to establish and update the coefficients therein.
Details of the coefficient setting circuit 506 will be described later on. Another equalizer will be described below with reference to FIG. 4 of the accompanying drawings. The equalizer shown in FIG. 4 is known as a decision-feedback equalizer (DFE).
The equalizer, generally denoted by 600 in FIG. 4, is substantially similar to the equalizer shown in FIG. 3, and has a transversal filter 602, a symbol determining circuit 603, a subtractor 605, and a tap coefficient setting circuit 606. The tap coefficient setting circuit 606 operates in the same manner as the tap coefficient setting circuit 506.
The equalizer 600 shown in FIG. 4 differs from the equalizer 500 shown in FIG. 3 with respect to the arrangement of the transversal filter 602. The transversal filter 602 shown in FIG. 4 comprises a section for being supplied with input signals and a section for being supplied with an output signal from the symbol determining circuit 603.
The section for being supplied with an input signal comprises a plurality of delay elements T.sub.1 .about.T.sub.m-1 for delaying an input signal supplied from a signal input terminal 601, a plurality of tap lines t.sub.O .about.t.sub.m-1 extending respectively from the delay elements T.sub.1 .about.T.sub.m-1, a plurality of coefficient units h.sub.0 .about.h.sub.m-1 for multiplying tap output signals by respective coefficients, and a plurality of adders a.sub.1 .about.a.sub.m-1 for adding all weighted tap output signals.
The section for being supplied with an output signal from the symbol determining circuit 603 comprises a plurality of delay elements T.sub.m .about.T.sub.m+k-1 for delaying an output signal from the symbol determining circuit 603, a plurality of tap lines t.sub.m .about.t.sub.m+k-1 extending respectively from the delay elements T.sub.m .about.T.sub.m+k-1, a plurality of coefficient units h.sub.m .about.h.sub.m+k-1 for multiplying tap output signals by respective coefficients, and a plurality of adders a.sub.m .about.a.sub.m+k-1 for adding all weighted tap output signals and adding the sum to the tap output signals from the adders a.sub.1 .about.a.sub.m-1.
FIG. 5 of the accompanying drawings shows still another equalizer.
The equalizer, generally denoted by 700 in FIG. 5, comprises a signal input terminal 701, a transversal filter 702, a series estimating circuit 703, a signal output terminal 704, a subtractor 705, and a tap coefficient setting circuit 706.
An output signal from the series estimating circuit 703 is supplied to an input terminal of the transversal filter 702, and successively delayed by delay elements T.sub.1 .about.T.sub.n-1. The delayed signals are extracted as parallel tap output signals from the delay elements T.sub.1 .about.T.sub.n-1, and multiplied by coefficients by corresponding tap coefficient units h.sub.0 .about.h.sub.n-1. The weighted tap output signals from the tap coefficient units h.sub.0 .about.h.sub.n-1 are added into a signal (l) which is output from the transversal filter 702.
The output signal (l) from the transversal filter 702 is applied to the subtractor 705, which calculates the difference between the output signal (l) and a received signal input to the signal input terminal 701. The subtractor 705 then supplies a differential signal (m) to the series estimating circuit 703.
The differential signal (m) from the subtractor 705 is also supplied to the tap coefficient setting circuit 706. Based on the differential signal (m) from the subtractor 705 and the tap output signals from the transversal filter 702, the tap coefficient setting circuit 706 estimates tap coefficients for the tap coefficient units h.sub.0 .about.h.sub.n-1, generates control signals to establish tap coefficients for the tap coefficient units h.sub.0 .about.h.sub.n-1, and supplies the control signals to the tap coefficient units h.sub.0 .about.h.sub.n-1 to establish tap coefficients therein.
The equalizers incorporating three respective transversal filters have been described above with reference to FIGS. 3, 4, and 5. Either one of these equalizers is arranged to update next tap coefficients based on differential signals between a tap input signal and a differential signal between a convolutional sum of tap coefficients and a reference signal.
The equalizers shown in FIGS. 3, 4, and 5 differ from each other depending on what the tap input signal, the reference signal, and the tap coefficients correspond to. Table 1 below shows details of these equalizers to which the tap input signal, the reference signal, and the tap coefficients correspond.
TABLE 1 ______________________________________ Tap input Reference Tap coeffi- signal signal cients ______________________________________ Linear equal- Received Transmitted Inverse trans- izer (LE) signal symbols mission path characteris- tics Decision-feed- * Received Transmitted * Inverse back equalizer signal symbols transmission (DFE) * Transmitted path charac- symbols teristics * Transmission path charac- teristics Equalizer with Transmitted Received Transmission series symbols signal path charac- estimation teristics ______________________________________
The tap coefficient setting circuit in each of the above equalizers will be described below.
As shown in FIG. 6 of the accompanying drawings, the tap coefficient setting circuit is supplied with a tap input signal and a differential signal (representing the difference between a reference signal and an output signal from a transversal filter), and outputs tap coefficients.
FIG. 6 shows only one tap input terminal and only one output terminal for outputting an established tap coefficient. Actually, as shown in FIGS. 3, 4, and 5, there are as many tap input terminals and as many output terminals as the number of coefficient units.
As shown in FIG. 6, the tap coefficient setting circuit has a first input terminal 801 as a tap input terminal, a second input terminal 802, a multiplier 803, an amplifier 804, an accumulating circuit 805, and an output terminal 808. The first input terminal 801 is connected to a tap line extending from each of the series-connected delay elements of the transversal filter. The second input terminal 802 is supplied with a differential signal which represents either the difference between an output signal from a symbol determining circuit and an output signal from the transversal filter, or the difference between an input signal of the equalizer and an output signal from the transversal filter, or the difference between a reference signal and an output signal from the transversal filter.
The multiplier 803 multiplies the tap input signal supplied from the first input terminal 801 by the differential signal supplied from the second input terminal 802. The amplifier 804 amplifies an output signal from the multiplier 803 with an amplification factor of .mu..sub.1. The accumulating circuit 805 accumulates signals supplied from the amplifier 804 in each Z.sup.-1 (Z=e.sup.i.omega.T, identical to the delay time of each delay element of the transversal filter). The output terminal 808 is connected to each of the control terminals of the coefficient units of the transversal filter.
The accumulating circuit 805 comprises an adder 806 and a delay circuit 807. The delay circuit 807 delays an output signal from the adder 806 for a period of time which is the same as the delay time of each delay element of the transversal filter. The accumulating circuit 805 serves to add a discrete signal inputted with a delay time equal to the sampling period to an accumulated value of signals that have been input prior to the discrete signal.
Operation of the equalizer and the tap coefficient setting circuit described above will briefly be described below.
If it is assumed in FIG. 3 that the transversal filter 502 has an order N, an input signal x.sub.j at a time jT (j=0, 1, 2, . . . , N; T represents a sampling period), and a weighting coefficient a.sub.i,j (i=0, 1, 2, . . . , N), then the transversal filter 502 produces an output signal y.sub.j expressed by: ##EQU1## If a weighting coefficient vector A.sub.j and an input signal vector X.sub.j are represented respectively by: EQU A.sub.j =[a.sub.0,j, a.sub.1,j, . . . , a.sub.A,j ].sup.T, EQU X.sub.j =[x.sub.j, x.sub.j-1, . . . , a.sub.j-N ].sup.T,
then the output signal from the transversal filter 502 can be expressed by: EQU Y.sub.j =A.sub.j.sup.T X.sub.j =X.sub.j.sup.T Z.sub.j.
If a target signal value (reference signal or the output signal from the symbol determining circuit 503 in FIG. 3) at this time is represented by d.sub.j, then the differential signal output from the subtractor 505 is given by .epsilon..sub.j =d.sub.j -y.sub.j =d.sub.j -A.sub.j.sup.T X.sub.j. The differential signal .epsilon..sub.j is supplied to the second input terminal 802 shown in FIG. 6, whereas the input signal vector X.sub.j is supplied to the first input signal 801. The input signal vector X.sub.j supplied to the first input signal 801 and the differential signal .epsilon..sub.j supplied to the second input terminal 802 are multiplied by the multiplier 803, and the sum signal is then amplified .mu..sub.1 times by the amplifier 804, which produces an output signal .mu..sub.1 .epsilon..sub.j X.sub.j.
The output signal .mu..sub.1 .epsilon..sub.j X.sub.j from the amplifier 804 is added by the adder 806 to a prior tap coefficient. Therefore, a newly established tap coefficient is given as A.sub.j+1 =A.sub.j +.mu..sub.1 .epsilon..sub.j X.sub.j.
The tap coefficient thus established is supplied to the control terminal of the corresponding coefficient unit of the transversal filter. As a result, the weighting by the coefficient unit is varied to optimize the filter characteristics of the transversal filter.
Each of the above equalizers is roughly divided into a transversal filter section and a control section. The transversal filter section is composed of delay elements T.sub.1 .about.T.sub.n-1 for holding an identifying time and a train of successive pulses across the identifying time, weighting circuits (coefficient units h.sub.0 .about.h.sub.n-1) connected to the delay elements T.sub.1 .about.T.sub.n-1, and adders a.sub.1 .about.a.sub.n-1 for combining output signals from the weighting circuits. When each of these equalizers is used in a receiving system of a transmission system for transmitting a signal that has been modulated by .pi./4-shift DQPSK, the weighting coefficients thereof are established to minimize an intersymbol interference produced at an identifying time due to fading.
Specifically, the tap weighting quantities of a transversal filter are set to an optimum value according to a training signal. The magnitude of tap coefficients are established by a tap coefficient setting circuit as shown in FIG. 6, based on a signal representative of an accumulation at a sampling period of products of signals applied to the taps of the delay elements, and differential signals between a reference signal and an output signal from the transversal filter.
Therefore, the above equalizers are slow in response and hence tend to be unable to adapt themselves to rapidly changing transmission path characteristics.